1. Field of the Invention
The invention relates to a semiconductor integrated circuit (IC), and in particular to a seal ring structure which can prevent electrostatic discharge damage in a semiconductor integrated circuit.
2. Description of Prior Art
Currently, an electrostatic discharge design is quite important in all semiconductor IC designs and fabrications. Since the size of electronic devices has decreased markedly and the density of ICs is continuously increasing, devices having tiny structures do not possess electrostatic discharge robustness. Therefore, how to prevent electrostatic discharge damage or provide sufficient capability to discharge an electrostatic charge is a major task in improving the reliability and yield of such products.
According to the concept of conventional electrostatic discharge design, a circuit that functions to discharge a large amount of electrostatic current and to stop high potential is disposed between an IC and the environment (for example, on a bonding pad). In addition, the area of the above-mentioned circuitry is maximized so as to allow a large amount of electrostatic current to flow, such that the electrostatic current can be discharged outside of the IC, thereby protecting the internal circuitry of the IC from damage.
Based on the design principle mentioned above, a conventional electrostatic discharge protection circuit connected to a bonding pad is fabricated by an additional doped diffusion region formed on a substrate. FIG. 1 illustrates a structure of a conventional electrostatic discharge protection circuit, while FIG. 2 depicts its equivalent circuit. In FIG. 1, a bonding pad 10 is connected to a doped diffusion region 25 on a substrate 20. In FIG. 2, a diode 27 providing an electrostatic discharge function is formed by the doped diffusion region 25 and by a well region 22. Since the diode breaks down upon the application of a high bias voltage to release a large amount of electrostatic current, it can greatly enhance the electrostatic protection ability.
However, the electrostatic discharge protection circuit is disposed on a region where no devices are formed on the substrate, thus occupying excessive space and not readily enlarging the efficient area of the protection circuit for discharging the electrostatic current. Hence, in the past, parasitic circuit(s) or SCR(s) have been adopted in an electrostatic discharge protection circuit to achieve a best performance in a given area.
Furthermore, a seal ring structure is a very important part in the back-end of a semiconductor process. The seal ring is a stress protection structure around an IC and can protect the internal circuit inside a chip from damage during a chip scribe line region treatment.
FIG. 3 illustrates a cross section diagram of a conventional seal ring, comprising metal layers 31-38, dielectric layers 40-47, via 7 and 51, silicide 52, P-type doped diffusion region, and a P-type substrate 200. The metal layer 31 is electrically connected to the P-type doped diffusion region 102. The metal layers 31-38 are electrically connected, and a Ohmic contact is between the metal layer 31 and the P-type doped diffusion 102, such that the potential of the metal layers 31-38 and the P-type substrate have the same voltage.
Moreover, the seal ring only provides a mechanical protection function. The conventional seal ring does not provide an electrostatic discharge protection function.
In view of the above, the present invention provides a seal ring structure having an electrostatic discharge protection function occupying a small amount space and efficiently discharging an electrostatic force.
Furthermore, the seal ring structure having an electrostatic discharge protection function according to the invention not only efficiently discharges the electrostatic force between a high power source and low power source in an IC, but also acts as a noise filter for the IC during a normal operation.
The seal ring structure having an electrostatic discharge protection function according to the invention is fabricated on a conductive first type substrate having a bias voltage provided by a second power source. The seal ring structure includes a conductive second type doped diffusion region on the conductive first type substrate, and a conductive metal structure, which comprises at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.
A method of fabricating the seal ring of the present invention comprises the following steps: providing a conductive first type substrate, forming a conductive second-type doped diffusion region located on the conductive first-type substrate, and forming a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.